Synopsys Off Campus Hiring Fresher For Formal Verification Engineer | Jobs Addaa | Limited Seats

Synopsys Off Campus Drive : Synopsys Off Campus hiring fresher for Formal Verification Engineer Role for B.E / B.Tech / M.E / M.Tech degree graduates and any degree batch graduates are eligible. The detailed company eligibility and application details are given below.  

About Synopsys :

Drive technology innovations that shape the way we live and connect. Our technology drives the Era of Pervasive Intelligence, where smart tech and AI are seamlessly woven into daily life. From self-driving cars and health-monitoring smartwatches to renewable energy systems that efficiently distribute clean power, Synopsys creates high-performance silicon chips that help build a healthier, safer, and more sustainable world.

Job Description :

You are a dedicated and detail-oriented Formal Verification Engineer with a passion for ensuring the reliability and functionality of complex design IPs. You excel in a collaborative environment, working closely with designers, architects, and verification engineers to drive verification projects to success. You possess a solid understanding of hardware micro-architecture and design, and you are proficient in HDLs like Verilog and SystemVerilog. Your problem-solving skills are top-notch, and you are familiar with formal property verification concepts and tools. You are eager to contribute to a team that is at the forefront of technological innovation and excellence.

Job Title : Formal Verification Engineer
Job Type : Full Time
Location : Bangalore
Experience : Fresher

Role and Responsibility :

• Helping decide on the best applications of formal verification techniques to various parts of the design.
• Reviewing functional and micro-architectural specifications to define the scope for formal verification.
• Creating high-quality formal verification test plans to sign off on the corresponding design implementation.
• Building formal verification testbenches, coding assertions and constraints, and applying abstraction techniques.
• Applying formal coverage techniques to analyze over-constraints and measure functional coverage.
• Collaborating closely with the Synopsys Tool Development Group to drive verification projects.

Education and Skills :

• Pursuing or completed BTech/MTech degree in Electrical Engineering, Computer Engineering, or a related field.
• Good understanding of hardware micro-architecture and design.
• Proficiency in HDLs like Verilog and SystemVerilog.
• Familiarity with SystemVerilog Assertions (SVA) and basic concepts of formal property verification.
• Good debugging and problem-solving skills.
• Scripting knowledge (Python/Perl/shell).
• Good interpersonal and communication skills and a dream to work as a great team member.

How To Apply Synopsys Off Campus Drive ??  

All interested and eligible candidates can apply before expire in the following link.  

Apply Link : Click Here