Synopsys Off Campus Hiring Fresher For R&d Engineering | Jobs Addaa | Limited Seats

Synopsys Off Campus Drive: Synopsys Off Campus hiring fresher for R&D Engineering Role for B.Tech or M.Tech degree graduates and any batch graduates are eligible. The detailed company eligibility and application details are given below.

About Synopsys :

Synopsys technology is at the heart of innovations that are changing the way people work and play. Self-driving cars. Machines that learn. Lightning-fast communication across billions of devices in the datasphere.

Job Description :

You are a driven and detail-oriented software engineer with a passion for digital logic and FPGA technology. You thrive in collaborative, cross-functional R&D teams where your ability to design and implement efficient algorithms and data structures is highly valued. You approach challenges with curiosity and a problem-solving mindset, eager to optimize complex systems and deliver high-performance solutions. Your solid foundation in computer science fundamentals, paired with your understanding of digital logic design and RTL flows, enables you to contribute meaningfully to the development and maintenance of industry-leading FPGA synthesis tools. 

Job Title : R&D Engineering
Job Type : Full Time
Location : Bengaluru
Experinence : Fresher

Role and Responsibility :

• Designing, developing, and maintaining large-scale software systems for FPGA logic synthesis, technology mapping, and timing optimization.
• Implementing efficient data structures and algorithms in C/C++ based on functional and technical specifications.
• Collaborating with product validation teams for test planning, execution, and providing customer support.
• Troubleshooting, debugging, and resolving issues in both new and existing features of the synthesis toolchain.
• Supporting and enhancing existing product features to improve performance and user experience.
• Engaging in cross-team discussions to share knowledge and drive continuous product improvement.

Education and Skills :

• B.Tech or M.Tech in Computer Science, Electrical Engineering, or related field from a reputed institute.
• Strong knowledge of data structures, graph algorithms, and C/C++ programming in Windows and/or Unix environments.
• Familiarity with digital logic design concepts and RTL (Verilog/VHDL) design flows.
• Understanding of timing constraints and static timing analysis.
• Working knowledge of FPGA design tools and flows is a plus.

How To Apply Synopsys Off Campus Drive ??  

All interested and eligible candidates can apply before expire in the following link.  

Apply Link : Click Here